12 March 1998 Implementing a real-time chain of segmentation of images on a multi-FPGA architecture
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Abstract
In this paper we present the study and the implementation of an optimized chain of segmentation operators. We implemented this chain in real time, consisting of a Deriche contour detection, double threshold, closing of contours and finally region labeling, on a multi-FPGA architecture. This architecture has four processing FPGAs and four memory modules. Deriche operator, closing of contours and labeling occupy each one an FPGA. Double threshold and detection of the extremities filled partially the forth FPGA. The slowest component of the chain is Deriche operator which can go up to 11.4 Mhz, assuring the process of an image every 40 ms. Deriche operator tries to extract the contours by assuming that a contour is a step super positioned by a white gaussian noise. Our implementation consists of a smoothing part of four second order filters and a Sobel as a derivation part. The second order filters are causal and non-causal horizontal and vertical operators. The gradient image passes through a double threshold filter to select the real contours and the crests and the background pixels. Closing of contours eliminates the false crests and finally the labeling gives a unique label to each closed region. The latency of the chain is in the order of three images. This implementation shows the efficiency of the chain and also it demonstrates the capabilities of our architecture as a prototyping system.
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Mohamed Akil, Mohamed Akil, Shahram Zahirazami, Shahram Zahirazami, } "Implementing a real-time chain of segmentation of images on a multi-FPGA architecture", Proc. SPIE 3303, Real-Time Imaging III, (12 March 1998); doi: 10.1117/12.302421; https://doi.org/10.1117/12.302421
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