Translator Disclaimer
26 March 1998 Cache parameters and memory power consumption of video algorithms
Author Affiliations +
Abstract
Energy efficient computing is growing in demand as portable systems require energy efficiency in order to maximize the battery life. Memory power consumption is becoming an increasingly larger fraction of the total power consumption of a given system. In this paper, we provide data and insight into how the choice of cache parameters affects memory power consumption of video algorithms. We make use of memory traces generated as a result of running typical MPEG- 2 motion estimation algorithms to simulate a large number of cache configurations. The cache simulation data is then combined with on-chip and off-chip memory power models to compute memory power consumption. We provide a detailed study of how varying cache size, block size, and associativity affects memory power consumption. The configurations of particular interest are the ones that optimize power under certain constraints. We also study the role of process technology in these experiments. In particular, we look at how moving to a more advanced process technology for the on-chip cache affects optimal points of operation with respect to memory power consumption.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bhanu Kapoor and Patrick W. Bosshart "Cache parameters and memory power consumption of video algorithms", Proc. SPIE 3311, Multimedia Hardware Architectures 1998, (26 March 1998); https://doi.org/10.1117/12.304671
PROCEEDINGS
9 PAGES


SHARE
Advertisement
Advertisement
RELATED CONTENT

IIA a novel method to optimize media instruction set...
Proceedings of SPIE (February 09 2006)
Single board H.261 video codec
Proceedings of SPIE (February 16 1995)
Implementing A 64kbit/s Video Codec On DSP Hardware
Proceedings of SPIE (January 29 1990)

Back to Top