100-nm CMOS gates patterned with 3 sigma below 10 nm

Hua-Yu Liu; Carlos H. Diaz; Chiu Chi; R. Kavari; Peng Cheng; Min Cao; Robert E. Gleason; Brian S. Doyle; Wayne M. Greene; G. Ray

doi:10.1117/12.309593

5 June 1998 100-nm CMOS gates patterned with 3 sigma below 10 nm

Hua-Yu Liu, Carlos H. Diaz, Chiu Chi, R. Kavari, Peng Cheng, Min Cao, Robert E. Gleason, Brian S. Doyle, Wayne M. Greene, G. Ray

Author Affiliations +

Proceedings Volume 3331, Emerging Lithographic Technologies II; (1998) https://doi.org/10.1117/12.309593
Event: 23rd Annual International Symposium on Microlithography, 1998, Santa Clara, CA, United States

Abstract

We have developed a process that uses a series of depositions and etches to pattern poly-silicon gates, eliminating the component of line width variation that normally arises from photolithography. Because the depositions and etches that determine line width are well controlled, we can pattern finer lines with better control using this process than with conventional methods. The results presented here show 3(sigma) < 10 nm for 100 nm lines. They are consistent with requirements for patterning gates in 2006 according to the 1997 edition of the National Technology Roadmap for Semiconductors. Using this patterning technique, we have made 100 nm nMOS transistors with 2 nm thick gate oxide, operating at 1.3 V. The distributions of important variables that characterize the operation of these transistors are shown to be much tighter than we obtain with conventional lithography.

Citation Download Citation

Hua-Yu Liu, Carlos H. Diaz, Chiu Chi, R. Kavari, Peng Cheng, Min Cao, Robert E. Gleason, Brian S. Doyle, Wayne M. Greene, and G. Ray "100-nm CMOS gates patterned with 3 sigma below 10 nm", Proc. SPIE 3331, Emerging Lithographic Technologies II, (5 June 1998); https://doi.org/10.1117/12.309593

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