8 June 1998 Nanometer-level metrology with a low-voltage CD SEM
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Abstract
This paper describes the application of a low-voltage scanning electron microscope (SEM) with nanometer-level accuracy for measurement in ultra-large-scale integration (ULSI). Minimum feature sizes of integrated circuits are expected to reach the 100-nm level and below (the nanometer region) in the near future. For the lithography process under that regime, precise critical dimension (CD) control and high resolution of resist patterns will be quite important for device fabrication, because variations in pattern sizes will degrade circuit performance. Therefore, metrology with nanometer-level accuracy is required for device fabrication under the regime. Here, we report on a CD-SEM that operates at 500 V to measure patterns at the 1 Gbit level. We used the S-8840 (Hitachi) to measure holes, lines/spaces, and the calibration standard (Micro-Scale). Several voltages from 500 V to 1000 V were used for the measurements. Static variation of less than 3 nm (3(sigma) ) was obtained in the pitch measurement of the Micro- Scale regardless of the acceleration voltages. For the holes, a lower voltage provided higher accuracy in static measurements. In the nanometer region, resist-pattern sizes microscopically fluctuate to the level of 10 nm due to the polymer characteristics of the resists (nano edge roughness). We could also characterize resist-pattern fluctuations with high accuracy. We compared our measurements with those from an atomic force microscope (AFM) for nanometer-level metrology, and conclude that at present CD-SEMs are more advantageous because of their higher accuracy and throughput.
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Toshiyuki Yoshimura, Makoto Ezumi, Tadashi Otaka, Hideo Todokoro, Jiro Yamamoto, Tsuneo Terasawa, "Nanometer-level metrology with a low-voltage CD SEM", Proc. SPIE 3332, Metrology, Inspection, and Process Control for Microlithography XII, (8 June 1998); doi: 10.1117/12.308768; https://doi.org/10.1117/12.308768
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