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As ASIC manufacture continues to evolve towards 0.35 micrometer, photolithography optimization becomes increasingly complex. I-line photolithography at these feature sizes results in proximity effects contributing to CD budgets and dominating the CD control. One of the critical levels of the current generation ASIC devices is the polysilicon gate level containing a set of lines in nesting configurations ranging from dense to isolated. The optical proximity effects of such geometries are pitch-dependent. Thus the key challenge of the gate level exposure is CD control of the features nested on a wide range of pitches. The state-of-the-art photolithography tools used for critical level manufacture are equipped with a wide range of illumination options including conventional, small-sigma, and off-axis. These options expand the exposure capabilities of steppers and complicate the optimization of the photolithography. The complexity of the image formation, coupled with the number of stepper exposure options, vastly expands the parameter space of photolithography optimization. The optimization of the photolithography process has to take into consideration the requirements of IC manufacture. These requirements include the CD tolerance, the depth of focus and the exposure latitude. The numeric value of each represents statistical and systematic factors influencing the yield of manufacture as well as the CD tolerance reflecting the IC performance goals. Our goal was to optimize the CD performance of critical level i-line photolithography. Our strategy combined resist model simulation and proof-of-principle testing. We analyzed a set of features with the nominal, pitch-independent CDs. We analyzed the CD range of variation for different pitches characteristic for the polysilicon gate level. The analysis was performed for a wide range of illumination/exposure conditions representing capabilities of the state-of-the-art, commercial i-line steppers. To qualify the exposure options, we have developed a metric taking into consideration the requirements of IC manufacture. We conducted systematic studies of the CD range versus illumination and exposure conditions. As a result, we identified the exposure strategies leading to the range of CD variation meeting the tolerance requirements of the ASIC manufacture. A methodology combining the resist image simulation and limited resist testing allowed us to find quickly the optimum exposure strategy supportive of manufacturing requirements. It also resulted in a great reduction of resources required to conduct the process characterization and the CD metrology. We applied this methodology to optimize the exposure condition of a current generation ASIC polysilicon gate level. The optimization methodology was verified experimentally. This discussion presents examples of optimization solutions. The report reviews the results of the resist modeling simulation, and reviews the results of the proof-of-principle metrology. We compare the modeling and the metrology and draw conclusions on the quality of the models' predictions. We interpret the model results in terms of CD characteristics of the critical level features exposed and developed in the resist. Finally, we assess the value of anchored resist simulation as a predictor of the CD characteristics.
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