29 June 1998 Evaluation of phase-edge phase-shifting mask for sub-0.18-μm gate patterns in logic devices
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Abstract
The speed of logic device is mainly dependent on gate length. To achieve process margin (DOF, E/T, etc.) and minimize On Chip Variation (OCV) of logic gate with sub 0.18 mm design rule, the need for phase-edge PSM technology that has the advantages of minimum resolution and Critical Dimension (CD) control has been increased. In this paper, performance and feasibility of phase-edge PSM technology were investigated. Using phase-edge PSM and positive resist process at DUV wavelength ((lambda) equals 248 nm), the possibility of 0.10 micrometer logic gate patterning was confirmed and 0.18 micrometer gate lines with DOF larger than 1.0 micrometer and plus or minus 6% CD variation were obtained. And design rules for phase-edge layout generation were extracted. Then the possibility of layout generation by the extracted design rules and layout conversion tool was confirmed. Also, the feasibility of mask CD uniformity and phase uniformity, and alignment between phase-edge mask and normal chrome (Cr) mask was investigated and confirmed. Considering lithographic performance and process feasibility, phase-edge PSM technology is a very promising method for patterning sub 0.18 micrometer gate in logic devices.
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DongHo Cha, Jongwook Kye, Nakgeuon Seong, Hoyoung Kang, Hanku Cho, Joo-Tae Moon, "Evaluation of phase-edge phase-shifting mask for sub-0.18-μm gate patterns in logic devices", Proc. SPIE 3334, Optical Microlithography XI, (29 June 1998); doi: 10.1117/12.310780; https://doi.org/10.1117/12.310780
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