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24 August 1998 Real-time multirate synchronous simulation with single and multiple processors
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It is well known that the efficiency of simulating large, complex dynamic systems can be significantly improved by using multi-rate integration, that is, by employing different integration frame rates for the simulation of fast and slow subsystem. Also, it is apparent that the overall speed of such simulations can be increased very significantly with the utilization of multiple processors. These considerations become especially important when the calculations must be run at real-time speed, as in hardware- in-the-loop simulations. However, there are significant issues regarding the scheduling algorithms for multi-rate integration within a single processor, as well as the data transfers between multiple processors. In this paper we show how these problems can be greatly simplified by letting each subsystem simulation run asynchronously with respect to other subsystem simulations, either using fixed or variable integration step sizes. Key to the successful implementation of both multi-rate integration and real-time, variable-step integration is the use of accurate extrapolation formulas to convert data sequences for one frame rate to another and to compensate for time mismatches and latencies in any real- time data sequences. Each processor in a multi-processor simulation can then be assigned to an identifiable subsystem or group of subsystems and run at its own frame rate, either fixed or variable. In this paper several examples of such simulations, both real time and non-real time, are presented. Utilization of the asynchronous methodology has the potential of greatly reducing the difficulties associated with interconnecting and testing many processors and hardware subsystems in a complex hardware-in-the-loop simulation.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Robert M. Howe "Real-time multirate synchronous simulation with single and multiple processors", Proc. SPIE 3369, Enabling Technology for Simulation Science II, (24 August 1998);


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