An innovative approach is being used to implement and simulate the IR and laser radar signal processing algorithms for the Advanced Sensor Technology Program and the Discrimination Interceptor Technology Program. Although the algorithms will run on four different computer architectures, they will use the same source code for all implementations. The initial development and testing will occur in Mathcad on a Windows 95/NT personal computer, then move to simulation on a Silicon Graphics workstation, then to scaled real-time simulation on a parallel high performance computer (HPC), and finally to the actual flight processor, the miniaturized parallel Wafer Scale Signal processor (WSSP) with a MIMD architecture. This flexibility is accomplished with code wrappers that implement interchangeable interface layers for the code modules, one wrapper for Mathcad matrices, one for C++ objects on the workstation, one for message passing with static routing on the HPC, and one for dynamically routed message passing on the WSSP. With this approach, developers can move modules back and forth from the workstation simulation environment to the implementation hardware. This will eliminate the need to maintain different versions of the same algorithm. The signal processing algorithms will be modified to work in a massively parallel architecture, with a message passing interface, which is simulated on the Silicon Graphics workstation, emulated on the HPC, and implemented on the WSSP. This approach will allow for pipeline processing as well as multiple, concurrently running instances of modules. In addition, innovative algorithms will fuse active laser radar detections and passive multicolor IR sensor measurements to improve target state estimation.