25 March 1998 Winner/loser-take-all circuits on SOI technology for neural network classification
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High connectivity of artificial neural network chip- embodiments combined with currently emerging 3-dimensionally stacked multichip modules for real-time applications of target classification require a scrutiny for low power technology insertion. Conventional CMOS high power consumption limits the allowable density of synapse/neuron elements. However Silicon-On-Insulator (SOI) technology has the potential for successful implementation of high density neural network because of the following unique features: (a) Operating voltage is reduced 3-fold from 5 to 1.5 volts, reducing power requirements by 9-fold; (b) Reduced substrate offers reduced capacitance and power and an increased speed; and, (c) Latch-up phenomenon is eliminated. Here we describe two practical winner/loser-take-all (W/LTA) circuits fabricated with 0.25 micrometer fully depleted SOI technology that are useful for neural networks and as compared to other such circuits offer considerable advantage of speed and performance. SPICE circuit simulations show that up to 9-bit resolution can be obtained between a winner and a loser input and with two cascaded circuits. Final characterization tests prove that constructing circuit elements from SOI technology would allow us to build large size neural networks for practical applications.
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Tuan A. Duong, Tuan A. Duong, Chris Saunders, Chris Saunders, Tri Ngo, Tri Ngo, Taher Daud, Taher Daud, } "Winner/loser-take-all circuits on SOI technology for neural network classification", Proc. SPIE 3390, Applications and Science of Computational Intelligence, (25 March 1998); doi: 10.1117/12.304827; https://doi.org/10.1117/12.304827

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