7 September 1998 Making the most of 15kλ2 silicon area for a digital retina PE
Author Affiliations +
Proceedings Volume 3410, Advanced Focal Plane Arrays and Electronic Cameras II; (1998) https://doi.org/10.1117/12.324004
Event: SYBEN-Broadband European Networks and Electronic Image Capture and Publishing, 1998, Zurich, Switzerland
Lodging a digital processing element (PE) in each pixel of a focal plane array is the challenge to be taken up to get programmable artificial retinas (PAR) that can be used in a large variety of applications. Using semi-static memory and communication structures together with charge sharing based computing circuitry, we elaborate a PE architecture of which the computational power versus area ratio improves over all previously known attempts. A key feature is the ability of neighbor PEs to be gathered into clusters allowing to get virtual memory through multigranularity computation. A 128 X 128 PAR, called PVLSAR 2.2, has been fabricated accordingly with 5 binary registers per PE. Each PE fits within a 15k(lambda) 2 silicon area$LR.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Fabrice Paillet, Fabrice Paillet, Damien S. Mercier, Damien S. Mercier, Thierry M. Bernard, Thierry M. Bernard, } "Making the most of 15kλ2 silicon area for a digital retina PE", Proc. SPIE 3410, Advanced Focal Plane Arrays and Electronic Cameras II, (7 September 1998); doi: 10.1117/12.324004; https://doi.org/10.1117/12.324004


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