7 September 1998 VLIW processor architecture adapted to FPAs
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Proceedings Volume 3410, Advanced Focal Plane Arrays and Electronic Cameras II; (1998) https://doi.org/10.1117/12.324008
Event: SYBEN-Broadband European Networks and Electronic Image Capture and Publishing, 1998, Zurich, Switzerland
Abstract
A new processor architecture intended to be integrated with a CMOS image sensor is presented. This association allows to design an intelligent camera that can perform on-chip image processing tasks. The processor is based on a VLIW architecture with a reduced instruction bus, able to execute multiple instructions in a parallel without any loss of performance. In addition, no more instruction cache is required, decreasing in this way the hardware complexity.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Laurent Petit, Laurent Petit, Jean-Didier Legat, Jean-Didier Legat, } "VLIW processor architecture adapted to FPAs", Proc. SPIE 3410, Advanced Focal Plane Arrays and Electronic Cameras II, (7 September 1998); doi: 10.1117/12.324008; https://doi.org/10.1117/12.324008
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