Development of a multi-FPGA netlist partitioner and a general-purpose graph partitioning system

Preeti Gowaikar; Millind Sohoni; M. Chandramouri; Sachin Patkar

doi:10.1117/12.328816

1 September 1998 Development of a multi-FPGA netlist partitioner and a general-purpose graph partitioning system

Preeti Gowaikar, Millind Sohoni, M. Chandramouri, Sachin Patkar

Proceedings Volume 3412, Photomask and X-Ray Mask Technology V; (1998) https://doi.org/10.1117/12.328816
Event: Photomask Japan '98 Symposium on Photomask and X-Ray Mask Technology V, 1998, Kawasaki City, Japan

Abstract

We describe here a general purpose graph partitioning system, especially suitable for VLSI applications. The partitioner has at its core a spectral based graph partitioner. In our strategy, the input netlist is first coarsened into a smaller netlist and the core spectral partitioner then proceeds to partition this coarsened netlist. This coarse partition is then lifted to a partition of the original netlist. The coarsener is fairly subtle and uses the theory of submodular functions, and of matchings. We also highlight some of our results.

Citation Download Citation

Preeti Gowaikar, Millind Sohoni, M. Chandramouri, and Sachin Patkar "Development of a multi-FPGA netlist partitioner and a general-purpose graph partitioning system", Proc. SPIE 3412, Photomask and X-Ray Mask Technology V, (1 September 1998); https://doi.org/10.1117/12.328816

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