A novel device structure for vertical bottom polysilicon (poly-Si) gate thin film transistors (TFTs) with dual-gate and offset structures is proposed. The new device, double- vertical-channel TFTs (DVC TFTs), allows suppression of leakage current and improvement of the photolithography limitation for large panel fabrication because of a deep- submicrometer channel length determined by the thickness of poly-Si gate. A 0.3 micrometers vertical-channel poly-Si TFTs is demonstrated on oxidized Si wafer. For low temperature poly- Si TFTs, several DVC TFTs processes are developed and demonstrated, including excimer laser annealing for the recrystallization of active layer and dopant activation.
Thomas W. Sigmon,
"New polysilicon thin-film transistors for leakage reduction", Proc. SPIE 3421, Display Technologies II, (17 June 1998); doi: 10.1117/12.311065; https://doi.org/10.1117/12.311065