17 June 1998 New polysilicon thin-film transistors for leakage reduction
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Proceedings Volume 3421, Display Technologies II; (1998) https://doi.org/10.1117/12.311065
Event: Asia Pacific Symposium on Optoelectronics '98, 1998, Taipei, Taiwan
Abstract
A novel device structure for vertical bottom polysilicon (poly-Si) gate thin film transistors (TFTs) with dual-gate and offset structures is proposed. The new device, double- vertical-channel TFTs (DVC TFTs), allows suppression of leakage current and improvement of the photolithography limitation for large panel fabrication because of a deep- submicrometer channel length determined by the thickness of poly-Si gate. A 0.3 micrometers vertical-channel poly-Si TFTs is demonstrated on oxidized Si wafer. For low temperature poly- Si TFTs, several DVC TFTs processes are developed and demonstrated, including excimer laser annealing for the recrystallization of active layer and dopant activation.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
In-cha Hsieh, In-cha Hsieh, Thomas W. Sigmon, Thomas W. Sigmon, } "New polysilicon thin-film transistors for leakage reduction", Proc. SPIE 3421, Display Technologies II, (17 June 1998); doi: 10.1117/12.311065; https://doi.org/10.1117/12.311065
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