10 November 1998 FILTRES128: front-end readout electronic development for silicon microstrip detectors
Author Affiliations +
We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 micrometers pitch. Each channel is composed of a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO which is read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes briefly the architecture of the circuit and presents test results of the 128 channel full chain chip before and after irradiation up to 10 Mrad.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Freddy Anstotz, Freddy Anstotz, Y. Hu, Y. Hu, J. Michel, J. Michel, J.-L. Sohler, J.-L. Sohler, D. Lachartre, D. Lachartre, } "FILTRES128: front-end readout electronic development for silicon microstrip detectors", Proc. SPIE 3445, EUV, X-Ray, and Gamma-Ray Instrumentation for Astronomy IX, (10 November 1998); doi: 10.1117/12.330292; https://doi.org/10.1117/12.330292


Design of a ROIC with 15um pitch for MWIR FPAs
Proceedings of SPIE (October 15 2015)
Using IDD to analyze analog faults and development of a...
Proceedings of SPIE (September 12 1996)
Design and preliminary results of APVD a fast low...
Proceedings of SPIE (November 10 1998)
Monolithic Lead Salt-Silicon Focal Plane Development
Proceedings of SPIE (November 30 1983)
Compensated digital readout family
Proceedings of SPIE (November 01 1991)

Back to Top