1 October 1998 Hardware implementation of image segmentation algorithm for real-time image compression
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Abstract
Segmentation algorithms are fast and simple technique used to obtain an image representation at different resolution levels, so they are widely used for image compression. Neither floating-point calculations nor large amounts of memory is required, so these algorithms can be easily implemented in relatively cheap and simple real-time systems. The proposed algorithm divides an image into rectangular blocks, which may overlap. The width and height of these blocks are set independently and can have optimal values from a preset range. Blocks are filled with a mean value of pixels from original image and their sizes are increased until the mean square error value for the block is smaller than the preset value. Next, the hardware implementation in single FPGA device is proposed. Paper also presents results obtained during off-line image compression. These results show better quality (in PSNR ratio) of restored images in compare to standard QuadTree algorithm. Simulations show that proposed hardware architecture can process standard monochrome CIF image with speed over 30 frames per second preserving low cost and high quality.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Piotr Wasilewski, "Hardware implementation of image segmentation algorithm for real-time image compression", Proc. SPIE 3460, Applications of Digital Image Processing XXI, (1 October 1998); doi: 10.1117/12.323163; https://doi.org/10.1117/12.323163
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KEYWORDS
Image processing algorithms and systems

Image segmentation

Image compression

Artificial intelligence

Field programmable gate arrays

Image quality

Image processing

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