Generally divider algorithms can be separated into two different kinds of algorithms, the multiplicative algorithms (MA) and the iterative digit recurrence algorithms (IDRA). The number of iterations of the MA and IDRA are proportional to log2 and the word-length, respectively. However every iteration of the MA consists of two multiplications and one addition, while the iteration period time of the IDRA only consists of one addition. The IDRA includes the SRT approach which does not require prescaling, and the GST approach which requires prescaling of the operands. The iteration period of the GST is much smaller due to the fact that the GST only examines three bits to predict the next quotient digit. Due to this reason, the overall latency of the GST-divider is shorter. Alternatively, by fixing the latency, the supply voltage of the GST can be reduced, resulting in a low power implementation. Thus, the GST is more suitable for low latency and low power applications.