22 May 1998 Latency requirements of optical interconnects at different memory hierarchy levels of a computer system
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Proceedings Volume 3490, Optics in Computing '98; (1998) https://doi.org/10.1117/12.308874
Event: Optics in Computing '98, 1998, Bruges, Belgium
Abstract
It is the ideal of a computer designer to have a huge, yet very fast memory connected to a uniprocessor core. But in reality, these two requirements, fast and huge, are not reconcilable. For this reason, a memory hierarchy was introduced that consists of very fast and small memory close to the processor core (the registers) but slower and larger memory further away from the processor (Figure 1). When data is needed, it is fetched from the slower memory into faster memory, from which it can be quickly accessed.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Henk Neefs, Henk Neefs, Pim Van Heuven, Pim Van Heuven, Jan M. Van Campenhout, Jan M. Van Campenhout, "Latency requirements of optical interconnects at different memory hierarchy levels of a computer system", Proc. SPIE 3490, Optics in Computing '98, (22 May 1998); doi: 10.1117/12.308874; https://doi.org/10.1117/12.308874
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