22 May 1998 Super scalar processor using chip-level optical interconnections
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Proceedings Volume 3490, Optics in Computing '98; (1998); doi: 10.1117/12.308900
Event: Optics in Computing '98, 1998, Bruges, Belgium
Abstract
With the prospect of a "billion transistor" microprocessor chip becoming a reality in the next decade, VLSI photonics will be an important technology for high bandwidth, chip level, I/O. In this paper we describe a system which demonstrates the use of free space optical channels to connect the functional units in a super scalar microprocessor. This approach enables architectures in which the number of functional units available for parallel instruction execution is significantly larger than can be implemented in a purely electronic design. The design is implemented with SEED devices, flip-chip bonded on a O.5prn CMOS silicon chip1 and is currently being fabricated as part ofthe 1997 CMOS-SEED Coop program2. In a super scalar microprocessor, high performance is achieved by executing multiple instructions in parallel. The architecture consists of multiple functional units, each capable of independent execution, with source and result operands delivered via local interconnection busses. During program execution, a control unit works on a buffer filled with instructions that are eligible for execution and selects those instructions that can be executed without a conflict for resources or data. For example, two instructions may be in conflict over a specific functional unit, a bus, or a port to memory or a register file. These types of conflicts are collectively referred to as structural hazards. There may also be a conflict caused by data dependence within a sequence of instructions. In other words, the operand of one instruction depends on the result of another. These are called data hazards. Other conflicts can be caused by uncertainty over the outcome of a conditional branch instruction. In this case it may be unknown whether or not a particular instruction will be executed at all. This is called a control hazard. These conflicts place a limit on the performance of super scalar machine by limiting the number of instructions that can be executed in parallel. In contemporary designs, architects have attempted to circumvent this limit by building additional functional units. This has an obvious impact on structural hazards but can also be effective on data and control hazards when speculative or redundant execution techniques are used3. For example, if a control hazard introduces uncertainty about the outcome of a conditional branch, both execution threads are allowed to proceed until the uncertainty is resolved. At that time, the computation from the untaken branch is simply discarded. Similarly data dependencies can be resolved by speculating as to the result of a dependent computation and discarding an execution thread ifthe guess was wrong. In general, the more speculative instruction execution that is possible, the greater the effective level of instruction parallelism. However, the number of functional units that can be built and connected on a single chip limits electronic designs. As an alternative, we are suggesting a design which implements free space optical channels as the interconnection busses in a multi-chip super scalar system. These high-speed interchip busses allow us to create systems where the number of functional units is significantly larger than can be implemented in a purely electronic design. In this paper we describe a prototype system which implements six integer functional units and three registers files in a three-chip super scalar ALU design. The control unit implements a subset of the MIPS RS-2000 instruction set architecture and is capable of full dynamic (runtime) scheduling ofALU resources. The rest of this paper is organized as follows. We begin with a logical description of the optical bus structure between the chips and the optoelectronic interface. This is followed by a description of the internal organization of the ALU chips. The optical system used to implement the optical interconnect is presented followed by simulation data showing the performance of the optical interconnect. Finally, we give a briefoutline ofour future research.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Donald M. Chiarulli, Steven Peter Levitan, R. P. Menon, N. Wattanapongsakorn, "Super scalar processor using chip-level optical interconnections", Proc. SPIE 3490, Optics in Computing '98, (22 May 1998); doi: 10.1117/12.308900; https://doi.org/10.1117/12.308900
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KEYWORDS
Optical interconnects

Beam splitters

Channel projecting optics

Optoelectronics

Clocks

Device simulation

Modulators

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