Advanced gate technology for sub-0.25-um CMOSFETs

Tsu-Jae King

doi:10.1117/12.323966

4 September 1998 Advanced gate technology for sub-0.25-μm CMOSFETs

Tsu-Jae King

Proceedings Volume 3506, Microelectronic Device Technology II; (1998) https://doi.org/10.1117/12.323966
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

As COOS technology is scaled into the sub-0.25 micrometer regime, the poly-Si gate depletion effect becomes more problematic. This paper discusses various technological approaches to eliminating this effect. It is shown that poly- SiGe is an especially promising alternative gate material because it can be integrated into an existing COOS process with relative ease. As compared to poly-Si gate technology, poly-Si_0.8Ge_0.2 gate technology provides improved resistance to the gate-depletion effect, improved tradeoff between the gate-depletion effect and the boron penetration problem for p-channel devices, and superior device reliability. The viability of poly-Si_0.8Ge_0.2 as a gate material for sub-0.25 micrometer COOS technology is demonstrated in the fabrication of 0.1 micrometer channel- length MOSFETs.

Citation Download Citation

Tsu-Jae King "Advanced gate technology for sub-0.25-μm CMOSFETs", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); https://doi.org/10.1117/12.323966

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available