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4 September 1998 Improving manufacturability of an rf graded channel CMOS process for wireless applications
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Abstract
Motorola's Graded Channel CMOS (GCMOS) provides a low cost and highly integrated solution for mixed-mode and RF applications. The GCMOS transistor has demonstrated performance advantages over standard CMOS processes with the same physical gate length. The graded channel, fabricated using lateral diffusion, provides a deep submicron Leff even with a gate length of 0.6 micrometer. The technology is constructed using a process that is fully compatible with standard CMOS manufacturing. However, in order to assure adequate threshold control, the lateral diffusions must be well-behaved. This means that both the channel implant and the source/drain implant must be truly self-aligned, requiring good control of the implants as well as the gate electrode profile. For aggressively designed GCMOS devices, small deviations of the implant beam from normal incidence can lead to unacceptable shifts in threshold. The sources of such error, and current industry standard machine tolerances for each, are discussed. Strategies for ensuring adequate control include a regimen of in-line process monitors, approximate error cancellation of the channel and source/drain implants, and the use of quadrature implants. By using these strategies a manufacturable process has been achieved.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Daniel J. Lamey, Troy Mackie, Han-Bin Liang, Jun Ma, Georges Robert, Craig Jasper, David Ngo, Ken Papworth, Sunny Cheng, Christy Wilcock, Rosemary Gurrola, Edward Spears, and Bruce Yeung "Improving manufacturability of an rf graded channel CMOS process for wireless applications", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); https://doi.org/10.1117/12.323961
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