Merged 2.5-V and 3.3-V 0.25-um CMOS technology

Isik C. Kizilyalli; Robert Y.S. Huang; D. Hwang; Brittin C. Kane; R. Ashton; S. Kuehne; X. Deng; Michael S. Twiford; E. P. Martin; D. Shuttleworth; K. Wittingham; S. Lytle; Yi Ma; Pradip K. Roy; Leonard J. Olmer; Hem Vaidya; F. Li; X. Li; Eric Persson; A. Massengale; L. Stirling; D. Chesire; K. Steiner; Rafael N. Barba; Morgan J. Thoma; William T. Cochran

doi:10.1117/12.323964

4 September 1998 Merged 2.5-V and 3.3-V 0.25-μm CMOS technology

Isik C. Kizilyalli, Robert Y.S. Huang, D. Hwang, Brittin C. Kane, R. Ashton, S. Kuehne, X. Deng, Michael S. Twiford, E. P. Martin, D. Shuttleworth, K. Wittingham, S. Lytle, Yi Ma, Pradip K. Roy, Leonard J. Olmer, Hem Vaidya, F. Li, X. Li, Eric Persson, A. Massengale, L. Stirling, D. Chesire, K. Steiner, Rafael N. Barba, Morgan J. Thoma, William T. Cochran

Author Affiliations +

Proceedings Volume 3506, Microelectronic Device Technology II; (1998) https://doi.org/10.1117/12.323964
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

In this paper a merged 2.5 V and 3.3 V high performance 0.25 micrometer CMOS technology is presented. Issues relevant to manufacturing, such as L_eff control and the impact of plasma-assisted back-end dielectric depositions on gate oxide reliability and isolation, are discussed. This technology features a 50 angstrom gate oxide, high-energy implant scheme, n⁺-polysilicon gate, and 4/5 levels of metal. An improvement of 1.45X in circuit performance and 4X in packing density is achieved over our 0.35 micrometer CMOS technology. The nominal ring oscillator delay time is 38(39) ps for 3.3(2.5) V operation.

Citation Download Citation

Isik C. Kizilyalli, Robert Y.S. Huang, D. Hwang, Brittin C. Kane, R. Ashton, S. Kuehne, X. Deng, Michael S. Twiford, E. P. Martin, D. Shuttleworth, K. Wittingham, S. Lytle, Yi Ma, Pradip K. Roy, Leonard J. Olmer, Hem Vaidya, F. Li, X. Li, Eric Persson, A. Massengale, L. Stirling, D. Chesire, K. Steiner, Rafael N. Barba, Morgan J. Thoma, and William T. Cochran "Merged 2.5-V and 3.3-V 0.25-μm CMOS technology", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); https://doi.org/10.1117/12.323964

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available