Optimized shallow trench isolation for sub-0.18-um ASIC technologies

Faran Nouri; Olivier Laparra; Harlan Sur; Samar K. Saha; Dipankar Pramanik; Martin Manley

doi:10.1117/12.323962

4 September 1998 Optimized shallow trench isolation for sub-0.18-μm ASIC technologies

Faran Nouri, Olivier Laparra, Harlan Sur, Samar K. Saha, Dipankar Pramanik, Martin Manley

Proceedings Volume 3506, Microelectronic Device Technology II; (1998) https://doi.org/10.1117/12.323962
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

An integrated shallow trench isolation process utilizing HDP (High Density Plasma) oxide and a highly manufacturable corner oxidation is described. The choice of trench corner oxidation temperature is shown to be critical in reducing silicon stress, and hence junction leakage, to the levels required by multi-million gate designs. This STI process is shown to be extremely robust and manufacturable. Optimal design of the trench depth and well profiles is shown to provide well-edge isolation adequate for sub-0.18 micrometer technologies.

Citation Download Citation

Faran Nouri, Olivier Laparra, Harlan Sur, Samar K. Saha, Dipankar Pramanik, and Martin Manley "Optimized shallow trench isolation for sub-0.18-μm ASIC technologies", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); https://doi.org/10.1117/12.323962

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