4 September 1998 Optimum junction depth design of the S/D extension regions (MDD) for sub-0.18-μm CMOS technologies
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Abstract
For scaled CMOS technologies, the source/drain-extension (MDD) junction depth (Xj) is important in achieving optimized device performance. According to the SIA roadmap, Xj is about 0.3 - 0.5 times the nominal gate length (Lgnom) for previous device generations as shown in Fig. 1. For devices with fixed Lgnom, shallower MDD can improve the short channel effects and the drive current sensitivity, however, trade-off occurs due to the increase in effective gate length and channel resistance. Various engineering techniques such as pocket implant can also change the requirement for Xj. It is therefore important to predict the Xj requirement for various transistor designs and facilitate faster turn-around time and minimize the design cost. In this work, a tuned 2-D MEDICI simulator is used to investigate the effect of Xj for 0.1 micrometer to 0.15 micrometer gate length devices. Effects of pocket implant and the use of an additional MDD spacer are compared. Both high performance (maximum off current equals lnA/micrometer) and low power (maximum off current equals 0.01nA/micrometer) devices are studied. For a given device design, an optimum Xj is found where the nominal drive current is maximized for fixed Lgnom and source/drain resistance (RSD). Key results are as following. (1) For high performance devices with pocket implant, the optimum Xj for S/D extension is approximately 300A (450A) for 0.1 micrometer (0.13 micrometer) Lgnom devices. Without pocket implant, the optimum Xj is reduced to approximately 250A (300A) which falls below the predicted lower limit of 0.3xLgnom. The improvement in the short channel roll-off by pocket implant allows the use of deeper junctions. Furthermore a 5% increase in nominal drive current is also observed for 0.1 micrometer devices with pocket implant. (2) The Xj requirement can be relaxed by using a thin MDD sidewall spacer. By adding a 200A MDD spacer, the optimum Xj for high performance device with pocket implant is approximately 450A and 550A for 0.1 micrometer and 0.13 micrometer node devices. However, addition of a MDD spacer will result in reduced gate overlap and hence larger RSD. It is found that a 200A spacer would result in an additional S/D resistance of 80 (Omega) for nMOS devices and cause 3 - 6% degradation in drive current. (3) For low power version devices with higher threshold voltage, Lgnom is adjusted to 0.11 micrometer and 0.15 micrometer while the minimum gate length (Lgmin) is set to be 85% Lgnom to account for the better short channel effects. The optimum Xj for low power devices with pocket implant is 250A (350A) for 0.11 micrometer (0.15 micrometer) Lgnom devices which is about 50 - 100A shallower than the Xj for high power devices. MDD spacer is more effective for low power devices and a 200A MDD spacer increases optimum Xj by 200A, matching the requirement for high power devices.
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Chih-Ping Chao, Manoj Mehrotra, Ih-Chin Chen, "Optimum junction depth design of the S/D extension regions (MDD) for sub-0.18-μm CMOS technologies", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); doi: 10.1117/12.323982; https://doi.org/10.1117/12.323982
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