Translator Disclaimer
4 September 1998 Prediction of deep submicron CMOS transistor performance and comparison with projected performance trends using tuned simulations
Author Affiliations +
Abstract
In this paper, a simulation study to predict the performance of CMOS technology in the deep sub-micron regime (0.20 micrometer down to 0.05 micrometer) is presented. The metric used to evaluate the CMOS transistor performance is a Figure of Merit (FOM). Using tuned process and device simulators, the performance FOM of bulk CMOS technologies were evaluated, with varying (1) gate lengths in the range of 0.05 - 0.20 micrometer, (2) power supply voltages (Vdd) of 1.0 - 1.8 V, (3) gate oxide thicknesses (Tox) of 20 - 40 A, (4) maximum off-state leakage currents of 0.01, 1 and 100 nA/micrometer, (5) different source/drain resistances and (6) different polysilicon doping levels. Vdd and Tox were scaled with gate length such that Vdd/Tox is fixed at about 5 MV/cm. It is found that it is increasingly difficult to keep the proportionality between performance FOM and 1/Lgate as the gate length is scaled to around 0.10 micrometer or below. This deviation is due to the decreasing trend of transistor drive current caused by the low supply voltages to be used and the nonscalability of VT. In order to try and improve the performance of CMOS technology, metal-gated Fully Depleted SOI CMOS transistors were evaluated in this study. It was found that although Fully Depleted Metal-Gate SOI provides an improvement in performance over conventional bulk CMOS technology, the FOM does not linearly scale with the gate length. The improvement in FOM obtained is almost entirely due to the smaller junction capacitance in SOI and not due to significantly increased drive currents in metal-gate FD-SOI when compared to conventional CMOS. Further, FOM performance falls short of the roadmap targets as the gate lengths are scaled below 0.10 micrometer just as in bulk CMOS. The effects of Off Current specifications and supply voltage on FOM were studied. It is shown that the CMOS performance can be improved by: (1) slightly increasing the supply voltage, and (2) using a dual- VT approach in which low-VT transistors are used in the critical path to improve circuit performance. With these approaches it is possible to extend the proportionality between FOM and 1/Lgate down to about 0.08 micrometer gate length.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
S. Sridhar, Chih-Ping Chao, Manoj Mehrotra, Mahalingam Nandakumar, and Ih-Chin Chen "Prediction of deep submicron CMOS transistor performance and comparison with projected performance trends using tuned simulations", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); https://doi.org/10.1117/12.323976
PROCEEDINGS
9 PAGES


SHARE
Advertisement
Advertisement
Back to Top