4 September 1998 Sub-half-micron device fabricated with 2-μm generation facilities
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Abstract
A MOS transistor with a channel length under 0.20 micrometer was developed with the process equipment typically utilized for a conventional 2 micrometer device. The transistor was built on the vertical side walls of a 3 dimensional trench, thus achieving much higher channel width W, and lower channel length L than possible using 2 micrometer planar technology. The capability of having larger W coupled with non- photolithography limited L, gives this vertical MOS transistor great advantages in drain current IDS, transconductance gm, and operation frequency fo over same technology planar transistors.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kiyoshi Mori, Kiyoshi Mori, } "Sub-half-micron device fabricated with 2-μm generation facilities", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); doi: 10.1117/12.323959; https://doi.org/10.1117/12.323959
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