The bitline contact hole and the storage node contact hole of 0.22 micrometers in 1G DRAM device manufacturing of 0.18 micrometers design rule were formed with thin nitride barrier self- aligned contact (TNBSAC) technology. In this work the isotropic dry etching process for the removal of nitride used as an oxide etching barrier in TNBSAC was characterized with respect to the parameters such as O2/(NF3 + O2) flow rate ratio, total flow rate, pressure, chiller temperature. From these tests, an isotropic nitride etching recipe was evaluated as the following: 0.8Torr 900Watt 60NF3 140O2 10 degrees C, nitride etch rate equals 1200 angstrom/min, selectivity of nitride to middle temperature oxide (MTO) equals 7.2, selectivity to Boro Phosphor Silicate Glass equals 7. When this condition was applied to TNBSAC technology, good etching characteristics was achieved enough to be implemented into device manufacturing like MTO loss less 100 angstrom on wordline corner, no Si substrate damage and contact hole CD bias about 160 angstrom. When the bitline contact hole and the storage node contact hole in 1G DRAM device fully processed form isolation to metallization were defined with TNBSAC technology, the electrical characterization of the bitline contact hole was investigated comparing TNBSAC with sidewall oxide spacer contact (SOSCON) technology. TNBSAC employing the isotopic nitride etching showed the short free connection, the lower junction leakage current and the lower contact resistance compared with SOSCON.