4 September 1998 Improved post-etch cleaning of dual-damascene system for 0.18-μm technology
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Abstract
A key challenge for 0.18 micrometer technology is the interconnect RC delay time, which becomes the limiting factor for device performance. This delay can be reduced by combining the use of a material of low dielectric constant between metal lines and the use of copper, which is a better conductor than aluminum. In this paper some of the difficulties of integrating these types of interconnects are discussed, and a new strategy for post dielectric etch cleaning is presented.
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Didier Louis, Didier Louis, Catherine Peyne, Catherine Peyne, Emile Lajoinie, Emile Lajoinie, B. Vallesi, B. Vallesi, David J. Maloney, David J. Maloney, Shihying Lee, Shihying Lee, } "Improved post-etch cleaning of dual-damascene system for 0.18-μm technology", Proc. SPIE 3508, Multilevel Interconnect Technology II, (4 September 1998); doi: 10.1117/12.324024; https://doi.org/10.1117/12.324024
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