28 August 1998 Bad vias are the cause for electrical test yield losses after plastic chip assembly
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Abstract
Faulty interlevel metal contacts are already a well known yield limiting factor in wafer processing. Yield losses at electrical wafer probe test due to single via fails have been reported several times. However, some of the latent via faults will pass the electrical wafer probe test undetected, but can fail in assembly or in real life. This will be quite expensive for the manufacturer. It is a must to prevent such bad vias or at least to detect them very early in the wafer manufacturing process to improve the 'time to money' situation for the IC-industry. The novel of this paper is a loss of function of single interlevel metal contacts during plastic packaging. This influences the final electrical test yield after packaging operation, while the electrical wafer probe test yield remains unaffected. Root cause analysis indicated that an interaction of different mechanisms led to this phenomenon.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Heinz Reiter and Othmar Leitner "Bad vias are the cause for electrical test yield losses after plastic chip assembly", Proc. SPIE 3510, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV, (28 August 1998); doi: 10.1117/12.324383; https://doi.org/10.1117/12.324383
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