28 August 1998 Copper chip technology
Author Affiliations +
Recently, IBM announced the first silicon integrated circuit technology that incorporates copper on-chip wiring. This technology, which combines industry-leading CMOS ULSI devices with 6 levels of hierarchically-scaled Cu metallization, has reached the point of manufacturing, after passing the qualification tests required to prove feasibility, yield, reliability, and manufacturability. The discussion of the change from Al to Cu interconnects for ULSI encompasses a wide variety of issues. This paper attempts to address these by way of example, from the broad range of detailed studies that have been performed in the course of developing these so-called 'copper chips'. Motivational issues are covered by comparative modeling of performance aspects and cost. The technology parameters and features are shown, as well as data relating to the process integration, electrical yield and parametric behavior, early manufacturing data, high-frequency modeling and measurements, noise and clock skew. The viability of this technology is indicated by results from reliability stressing, as well as the first successful demonstrations of fully functional SRAM, DRAM, and microprocessor chips with Cu wiring. The advantages of integrated Cu wiring may be applied even more broadly in the future. An example shown here is the achievement of very high-quality integrated inductors; these may help prospects for complete integration of RF and wireless communications chips onto silicon.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Daniel C. Edelstein, Daniel C. Edelstein, } "Copper chip technology", Proc. SPIE 3510, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV, (28 August 1998); doi: 10.1117/12.324379; https://doi.org/10.1117/12.324379


Copper chip technology
Proceedings of SPIE (August 27 1998)
Copper chip technology
Proceedings of SPIE (September 04 1998)
Copper chip technology
Proceedings of SPIE (September 03 1998)
Modeling limits of multilevel interconnect technology
Proceedings of SPIE (September 15 1995)
Copper chip technology
Proceedings of SPIE (September 04 1998)

Back to Top