28 August 1998 Yield-modeling accuracy requirements for 300-mm processing
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Semiconductor yield models and the targets based on these models often differ from actual yield performance. The purpose of this study is to investigate yield modeling accuracy risks and requirements for 180, 150, and 130 nm technologies. Using a 300 nm CMOS process with 4 layers of copper and conventional SiO2 dielectric, this analysis focuses on several significant risk costs including building cost, equipment cost, floor space cost, operating cost, scrap cost, and unused capacity cost. Our analysis resulted in several observations about yield modeling error.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Daren L. Dance, Daren L. Dance, Christopher W. Long, Christopher W. Long, } "Yield-modeling accuracy requirements for 300-mm processing", Proc. SPIE 3510, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV, (28 August 1998); doi: 10.1117/12.324382; https://doi.org/10.1117/12.324382

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