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8 October 1998 Alternative approaches implementing high-performance FIR filters on lookup-table-based FPGAs: a comparison
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Proceedings Volume 3526, Configurable Computing: Technology and Applications; (1998) https://doi.org/10.1117/12.327043
Event: Photonics East (ISAM, VVDC, IEMB), 1998, Boston, MA, United States
Abstract
Finite impulse response filters (FIR filters) are very commonly used in digital signal processing (DSP) applications and are traditionally implemented using ASICs or DSP-processors. For FPGA implementation, due to the high throughput rate and large computational power required under real-time constraints, they are a challenging subject. Indeed, the limitation of resources on FPGA, i.e., logic blocks and flip flops, and furthermore, the high routing delays, requires compact implementations of the circuits. Three approaches for implementation of high-performance symmetric FIR filters on lookup table-based FPGAs will be considered in this paper. Fully parallel distributed arithmetic, table lookup multiplication, and conventional hardware multiplication. Implementation results will be illustrated by an 8 taps 8 bits symmetric FIR filter, and comparative considerations of the above approaches invoked for Xilinx FPGAs will be also shown.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Tien-Toan Do, Holger Kropp, Carsten Reuter, and Peter Pirsch "Alternative approaches implementing high-performance FIR filters on lookup-table-based FPGAs: a comparison", Proc. SPIE 3526, Configurable Computing: Technology and Applications, (8 October 1998); https://doi.org/10.1117/12.327043
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