8 October 1998 Design and implementation of a high-level image processing machine using reconfigurable hardware
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Proceedings Volume 3526, Configurable Computing: Technology and Applications; (1998) https://doi.org/10.1117/12.327017
Event: Photonics East (ISAM, VVDC, IEMB), 1998, Boston, MA, United States
Abstract
Image Processing requires high computational power, plus the ability to experiment with algorithms. Recently, reconfigurable hardware devices in the form of Field Programmable Gate Arrays (FPGAs) have been proposed as a way of obtaining high performance at an economical price. At present, however, users must program FPGAs at a very low level and have a detailed knowledge of the architecture of the device being used. To try to improve design time for FPGA-based image processing, this paper reports on the design and realization of an FPGA-based image processing machine and its associated high level programming model. Central to the design of architecture blocks is the `design to fit' approach. The abstract machine is based on a PC host system with a PCI-bus add-on card containing Xilinx XC6200 series FPGA(s). The machine's high level instruction set is based on the operators of Image Algebra. XC6200 series FPGA configurations have been developed to implement each high level instruction.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Paul Donachy, Paul Donachy, Danny Crookes, Danny Crookes, Ahmed Bouridane, Ahmed Bouridane, K. Alotaibi, K. Alotaibi, Abdsamad Benkrid, Abdsamad Benkrid, "Design and implementation of a high-level image processing machine using reconfigurable hardware", Proc. SPIE 3526, Configurable Computing: Technology and Applications, (8 October 1998); doi: 10.1117/12.327017; https://doi.org/10.1117/12.327017
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