Lithography process simulation has proven to be a useful and effective tool for process characterization, namely, properly characterize critical dimension (CD) variations from the design that are caused by proximity effects and distortions introduced by the patterning tool, reticle, resist processing and etching. Accurate lithography process simulator further enables process engineers to automate the tasks of advanced mask design, verification and inspection that are used in deep-sub-micron semiconductor manufacturing. However, to get the most benefit from process simulations, we should properly calibrate the simulation model according to the process to be characterized. That is, given a representative set of CD measurements obtained from the process, we fine-tune the process model parameters so that the simulated/predicted CDs well match the measured CDs. By doing so, we can ensure to some extent that process simulations give sensible results to be used in the design analysis, verification and inspection applications. In this paper, we would like to demonstrate the possibility of obtaining an accurate process model for lithography process simulations via model calibration. We will also demonstrate the accuracy of calibrated process simulations by applying the calibrated model in mask defect printability analysis. For simplicity, the process model and the algorithms used in model calibration will not be discussed in this article but in our future publications. In Section 2, we present the characterization and calibration of a 0.18 micrometer DUV lithography process using positive chemically amplified resist (APEX-E) as an example. We describe the test pattern selections, the calibration process, and the performance of the calibrated model in terms of predicting the CD measurements given test patterns. In Section 3, we briefly describe the technology of defect printability analysis based on process simulations. We will demonstrate that with the help of calibrated process simulations, we can quite accurately predict the printabilities of various test defects.