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27 April 1999 Design and test of a CMOS camera with analog memory for synchronous image capture
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Implementation and test results of an array for image applications with full-frame analog memory is presented. The array was implemented using 1.0 micrometers double metal, single poly n-well standard CMOS technology. The sensor consists of a 24 by 24 pixels square array and circuitry for random access readout. A pixel is composed by a phototransistor and control circuitry to regulate the exposure time to light of phototransistors. Each pixel also includes an analog memory implemented using MOSFET capacitors. The output buffer drives the capacitance of the output line. The system requires a total core area of 5 mm2. Tests were performed for each individual pixels and for the complete array. The voltage output as a function of integration time under different illumination levels shows a linear behavior. Varying the exposure time is possible to change the detector sensitivity. The fixed pattern noise was 0.58 percent of saturation level. Memory capabilities were also tested, allowing non-destructive reading and a storage time over few seconds without a significant degradation.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Genis Chapinal, Mauricio Moreno, Sebastian A. Bota, Gemma Hornero, and Atila Herms "Design and test of a CMOS camera with analog memory for synchronous image capture", Proc. SPIE 3649, Sensors, Cameras, and Systems for Scientific/Industrial Applications, (27 April 1999);


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