21 December 1998 MPEG-4 video communication processor architecture
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Acceptable video quality in standards-based video communication requires the use of hardware acceleration. Traditional approaches to this in recent years have been a hardwired approach, in which video compression algorithms cannot be changed, and a fully programmable approach, in which a single VLIW processor is programmed in a high-level language (such as `C') or assembly. The drawback of the hardwired approach has been inflexibility and difficulty of adding performance enhancements since new silicon is needed to make improvements. The drawback of the fully programmable approach is the difficulty in developing software and tools for the processor. This has the new result of lengthening the overall design cycle time. A new approach, described in this paper, uses multiple VLIW processing elements, some of which are pipelined, that have reprogrammable microcode. This allows particular algorithm classes, such as DCT/IDCT, motion compensation or motion estimation, to be reprogrammed to improve performance without changing the silicon. First, overviews of a new MPEG4 Video Communication system architecture and its hardware synthesis process are given. Then, two methods for reprogramming the microcode for the motion estimator are discussed and compared. Finally, comparisons of our system architecture to the traditional hardwired architecture and the fully programmable architecture are given.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kathy Moseler, Kathy Moseler, Robert Chen, Robert Chen, Sami Levi, Sami Levi, "MPEG-4 video communication processor architecture", Proc. SPIE 3655, Media Processors 1999, (21 December 1998); doi: 10.1117/12.334754; https://doi.org/10.1117/12.334754


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