As the semiconductor roadmap continues to require imaging of smaller feature son wafers, we continue to explore new approaches in OPC strategies to extend the lifespan of existing technology. In this paper, we study a new OPC technology, called halftone biasing, and its application on an OPC characterization reticle, designed by MicroUnity Systems Engineering, Inc. The RTP9 test reticle is the latest in a series of 'LineSweeper' characterization reticles. Each reticle contains a wide range of line width sand pitches, each with several alternative OPC treatments, including references cases, scattering bars, and fine biasing. One of RTP9's design requirements was to support very fine, incremental biases for densely-pitched lines. Ordinarily, this would dictate a reduced address unit and with it the costly penalty of a square-law increase in e- beam write time. RTP9 incorporates a new OPC strategy, called halftone biasing, which has been proposed to address this problem. Taking advantage of optical reduction printing, this technique applies a sub-resolution halftone screen to the edges of figures to accomplish fine biasing equivalent to using an address unit one-fourth of the size of the actual e-beam writing grid. The resulting edge structure has some of the characteristics of aggressive OPC structures, but can be used in areas where traditional scattering bars cannot be placed. The trade-off between the faster write times achieved and the inflation of pattern file size is examined. The manufacturability and inspectability of halftone-biased lines on the RTP9 test reticle are explored. Pattern fidelity is examined using both optical and SEM tools. Printed 0.18 micrometers DUV resist line edge profiles are compared for both halftone and non- halftone feature edges. The CD uniformity of the OPC features, and result of die-to-database inspection are reported. The application of halftone biasing to real circuits, including the impact of data volume and saved write time, is also discussed.