23 April 1999 PN and SOI wafer flow process for stencil mask fabrication
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Proceedings Volume 3665, 15th European Conference on Mask Technology for Integrated Circuits and Microcomponents '98; (1999) https://doi.org/10.1117/12.346224
Event: 15th European Conference on Mask Technology for Integrated Circuits and Micro-Components, 1998, Munich, Germany
Abstract
Two process flows for the fabrication of stencil masks have been developed. The PN Wafer Flow- and the SOI Wafer Flow Process. Membranes and stencil masks out of different 6 inch Si base wafers with 3 micrometers membrane thickness and a membrane diameter between 120 mm and 126 mm were fabricated. The membrane stress depending on the material property and doping level has been determined. First metrology measurements have been carried out.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Joerg Butschke, Joerg Butschke, Albrecht Ehrmann, Albrecht Ehrmann, Ernst Haugeneder, Ernst Haugeneder, Mathias Irmscher, Mathias Irmscher, Rainer Kaesmaier, Rainer Kaesmaier, Karl Kragler, Karl Kragler, Florian Letzkus, Florian Letzkus, Hans Loeschner, Hans Loeschner, Josef Mathuni, Josef Mathuni, Ivo W. Rangelow, Ivo W. Rangelow, Carsten Reuter, Carsten Reuter, Feng Shi, Feng Shi, Reinhard Springer, Reinhard Springer, } "PN and SOI wafer flow process for stencil mask fabrication", Proc. SPIE 3665, 15th European Conference on Mask Technology for Integrated Circuits and Microcomponents '98, (23 April 1999); doi: 10.1117/12.346224; https://doi.org/10.1117/12.346224
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