20 July 1999 Digital-readout CMOS design for capacitive sensors using on-chip variable sense capacitor arrays
Author Affiliations +
Abstract
A digital readout design in CMOS technology is described for monolithic integration with microelectromechanical capacitive sensors using on-chip variable sense capacitor arrays with resolutions of 2.5 fF, 10 fF and 40 fF, respectively. The designed circuit produces a 4-bit digital readout proportional to the capacitive difference between the sense and the reference capacitors. The CMOS digital readout is compatible with +/- 1.5 V operation for low power consumption, uses a +1.5 V reference voltage with a switching speed of approximately 100 kHz. The digital readout design presented here is quite general and can be used in a wide variety of analog microsensors on the chip.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ashok Srivastava, Hanson Yong, Daniel Wildhaber, Mohammed Hasan, Vishnupriya Gongalreddy, Jing Wang, Pratul K. Ajmera, Farzad Pouralborz, "Digital-readout CMOS design for capacitive sensors using on-chip variable sense capacitor arrays", Proc. SPIE 3673, Smart Structures and Materials 1999: Smart Electronics and MEMS, (20 July 1999); doi: 10.1117/12.354284; https://doi.org/10.1117/12.354284
PROCEEDINGS
11 PAGES


SHARE
Back to Top