14 June 1999 Application of model-based lithographic process control for cost-effective IC manufacturing at 0.13 μm and beyond
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Abstract
The 0.13 micrometers semiconductor manufacturing generation, shipping as early as 2001, will have transistor gate structures as small as 100 nm, creating a demand for sub- 10nm gate linewidth control. Linewidth variation consists of cross-chip, cross-wafer, cross-lot, and run-to-run components, so we can expect the individual component requirements to be sub-5nm. For model-based, run-to-run control systems to achieve this level of performance, stabilization of lithographic focus will be critical. In this work we show promising results based upon a novel phase-shift focus monitor, optical overlay metrology, and robust analysis software. Extensions of this work explore spatial dependencies across the lithographic field due to reticle error and across the wafer due to wafer nanotopography. Both sources of variation can cause collapse of the focus-exposure process window near the limits of lithographic resolution, particularly for gate structures in high-performance microprocessors. Our work supports the contention that photolithography-induced defects may become the primary source of yield loss for the 0.13 micrometers generation and beyond.
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Kevin M. Monahan, Kevin M. Monahan, Patrick J. Lord, Patrick J. Lord, Clive Hayzelden, Clive Hayzelden, Waiman Ng, Waiman Ng, } "Application of model-based lithographic process control for cost-effective IC manufacturing at 0.13 μm and beyond", Proc. SPIE 3677, Metrology, Inspection, and Process Control for Microlithography XIII, (14 June 1999); doi: 10.1117/12.350830; https://doi.org/10.1117/12.350830
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