In this work, die-to-die CD-variations across a wafer are investigated as a potential important contribution to the global gate CD-control. Measuring the non-uniformity in different experiments using CD-SEM and ELM revealed different parameters, impacting the measured non-uniformity value. It will be pointed out that the measurement itself can have a significant contribution to the measured 3(sigma) -value, especially using CD-SEM, if the level in non-uniformity is low. Further on, it will be shown that the choice of resist and developer chemistry can have a high impact on the i-W CD non-uniformity. Moreover, the potential impact of exposure and track processing will be outlined, and an optimization methodology will be presented. Finally, it will be shown that gate process integration, in particular BARC- and POLY-etching, is increasing the i-W CD non-uniformity. This is affecting the ELM-results, despite the high precision and repeatability of these measurements. This ELM-variation, as well as the overall i-W CD non- uniformity should be taken into account when using ELM or CD-SEM as a metrology tool for process window characterization.