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26 July 1999 Systematic approach to correct critical patterns induced by the lithography process at the full-chip level
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This paper present a systematic approach to correct critical patterns, which are more prone to defects due to the photo lithography process, at the full-chip level for sub-quarter micron CMOS applications. In the first stage of the photo lithography process for integrated circuits (IC), the bridging failure between patterns in a photoresist layer has been found occasionally. The small process margin in patterning plays a key part of the device yield drop, when process conditions or production lines are changed. However, it is a very difficult and time-consuming job to find and correct all the possible critical patterns which might cause failure. Test patterns with various line-and-spaces are designed and simulated using the aerial image model and the third order polynomial function of critical patterns. The DRC software with the rules searches an entire area of the IC layout. The proposed approach to extract critical patterns is cost effective and fast compared to the evaluation of a layout using a photo lithography simulator at the full-chip level. Applying this methodology to 256M DRAM with 0.25 micrometers minimum design width in the periphery and core area, all bridge defects found before correction can be removed. Furthermore, it will be a useful tool to the product engineer who should indicate monitoring patterns, which are sensitive to the lithography process margin.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chul-Hong Park, Yoo-Hyon Kim, Ji-Soong Park, Kwan-Do Kim, Moon-Hyun Yoo, and Jeong-Taek Kong "Systematic approach to correct critical patterns induced by the lithography process at the full-chip level", Proc. SPIE 3679, Optical Microlithography XII, (26 July 1999);


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