10 March 1999 Chip-level three-dimensional assembling of microsystems
Author Affiliations +
Proceedings Volume 3680, Design, Test, and Microfabrication of MEMS and MOEMS; (1999) https://doi.org/10.1117/12.341260
Event: Design, Test, and Microfabrication of MEMS/MOEMS, 1999, Paris, France
We propose a new method of assembling 3D microsystems by means of chip level electrical interconnection. Silicon dies are flip-chipped out of a silicon wafer by using ICP-RIE instead of a dicing saw. Fringes of the chips are patterned into pin-shapes so that they can be vertically inserted into the micro motherboard for electrical and physical connection. The pins are coated with Cr-Au, and the contact pads are electroplated with Cu for low contact resistance. the pins are tapered in width, and assembling was easily done by manual positing under the optical binocular microscope. This technique is a break through to the hybrid integration of various kinds of micro chips independent of materials or fabrication compatibility.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hiroshi Toshiyoshi, Hiroshi Toshiyoshi, Yoshio Mita, Yoshio Mita, Minoru Ogawa, Minoru Ogawa, Hiroyuki Fujita, Hiroyuki Fujita, } "Chip-level three-dimensional assembling of microsystems", Proc. SPIE 3680, Design, Test, and Microfabrication of MEMS and MOEMS, (10 March 1999); doi: 10.1117/12.341260; https://doi.org/10.1117/12.341260


Design techniques for surface-micromachining MEMS processes
Proceedings of SPIE (September 19 1995)
Reproducibility data on SUMMiT
Proceedings of SPIE (August 30 1999)
Analysis of stress-driven delamination in contact vias
Proceedings of SPIE (September 12 1996)
Novel through-die connections for MEMS applications
Proceedings of SPIE (January 15 2003)

Back to Top