24 August 1999 Performance modeling in ATR algorithm and data partitioning
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Proceedings Volume 3718, Automatic Target Recognition IX; (1999); doi: 10.1117/12.359977
Event: AeroSense '99, 1999, Orlando, FL, United States
One of the problems with taking aided target recognizer software written for a uniprocessor and hosting it on a multiprocessor running in real time is determining the allocation of data and functions across multiple processors. The partitioning varies based on the algorithm and the computer architecture. Often, more than one partitioning is possible. Ideally, one would like to evaluate the possible partitioning, choose a one that meets requirements, and modify or rewrite the existing program to embody that partitioning. The paper describes the steps that were used to rehost a real aided target recognition algorithm onto a commercial off-the- shelf embedded multiprocessor, with an emphasis on the use of performance modeling to determine which partitioning schemes will result in code which meets requirements. Libraries that facilitate the transition from uniprocessor to multiprocessor are also discussed; the libraries are being evaluated as part of an NVESD effort for the High Performance Computing Modernization Office.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Dolores A. Shaffer, "Performance modeling in ATR algorithm and data partitioning", Proc. SPIE 3718, Automatic Target Recognition IX, (24 August 1999); doi: 10.1117/12.359977; https://doi.org/10.1117/12.359977


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