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12 March 1999 ELIPS: toward a sensor fusion processor on a chip
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Abstract
The paper present the concept and initial test from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) processor is developed to seamlessly combine rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor in compact low power VLSI. The first demonstration of the ELIPS concept targets interceptor functionality; other applications, mainly in robotics an autonomous system are considered for the future. The main assumption behind ELIPS is that fuzzy, rule-based and neural forms of computation can serve as the main primitives of an 'intelligent' processor. Thus, in the same way classic processors are designed to optimize the hardware implementation of a set of fundamental operations, ELIPS is developed as an efficient implementation of computational intelligence primitives, and relies on a set of fuzzy set, fuzzy inference and neural modules, built in programmable analog hardware. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Following software demonstrations on several interceptor data, three important ELIPS building blocks have been fabricated in analog VLSI hardware and demonstrated microsecond-processing times.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Taher Daud, Adrian Stoica, Tyson Thomas, Wei-te Li, and James A. Fabunmi "ELIPS: toward a sensor fusion processor on a chip", Proc. SPIE 3719, Sensor Fusion: Architectures, Algorithms, and Applications III, (12 March 1999); https://doi.org/10.1117/12.341343
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