Paper
23 April 1999 Characterization of gate electrode etch process for 0.25 μm extended to 0.18 μm
Henry Gerung, Vijay Chhagan, Pradeep R. Yelehanka, Mei-Sheng Zhou, Joe K. Hui
Author Affiliations +
Proceedings Volume 3742, Process and Equipment Control in Microelectronic Manufacturing; (1999) https://doi.org/10.1117/12.346233
Event: Microelectronic Manufacturing Technologies, 1999, Edinburgh, United Kingdom
Abstract
With shrinking dimension of the transistor gate, the gate profile and line dimension control requirement becomes more stringent. LPCVD (Low Pressure Chemical Vapor Deposition) polysilicon is used as the gate material with thermally grown thin nitrided gate oxide. Bottom Anti-Reflective Coating is used together with Deep UV resist for patterning. After etch, footing at the gate bottom is observed and the resulting in-line line width has a large degree of non- uniformity. These phenomena are found on both 0.25 micrometers and 0.18 micrometers structure. In this paper, we present the application of Design of Experiment principle in solving footing problem at the bottom of the gate polysilicon and obtaining better in-line control.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Henry Gerung, Vijay Chhagan, Pradeep R. Yelehanka, Mei-Sheng Zhou, and Joe K. Hui "Characterization of gate electrode etch process for 0.25 μm extended to 0.18 μm", Proc. SPIE 3742, Process and Equipment Control in Microelectronic Manufacturing, (23 April 1999); https://doi.org/10.1117/12.346233
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KEYWORDS
Etching

Diffractive optical elements

Semiconducting wafers

Critical dimension metrology

Oxides

Photoresist materials

Electrodes

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