27 April 1999 Floorplanning of memory ICs: routing complexity vs. yield
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Proceedings Volume 3743, In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing; (1999); doi: 10.1117/12.346926
Event: Microelectronic Manufacturing Technologies, 1999, Edinburgh, United Kingdom
Abstract
It has recently been shown that for very large chips, especially those with some incorporated redundancy, the chip's floorplan may affect its yield. When selecting a floorplan, the designer should, therefore, consider the expected yield in addition to the traditional objectives such as area, performance, and routing complexity. This paper studies the two seemingly unrelated objectives of routing complexity minimization and yield maximization, and justifies the need for a trade-off analysis when determining the floorplan. We will focus on the analysis of large memory ICs with redundant modules, for which several alternative floorplans may exist.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Israel Koren, Zahava Koren, "Floorplanning of memory ICs: routing complexity vs. yield", Proc. SPIE 3743, In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing, (27 April 1999); doi: 10.1117/12.346926; https://doi.org/10.1117/12.346926
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