For planarization of interlevel dielectric between two wiring layers, chemical mechanical polishing (CMP) is used from 0.25 micrometer devices. Here, in order to improve global planarity, dummy patterns area added to the original wiring patterns. In the conventional dummy generation system, because the all wiring patterns are oversized geometrically to obtain CMP area, the geometrical oversizing consumes a long time. In order to reduce the time of geometrical oversizing, minimum CMP area and maximum CMP area, which is calculated faster than geometrical oversizing, are introduced in the new data processing. At first, instead of the geometrical oversizing, the total area of patterns (minimum CMP area) and the total area of individually oversized patterns (maximum CMP area) are calculated at each small region in wiring layer. Then dummy generation regions are selected by using these two total area. When all of surroundings of a small region are decided to be dummy generation region or not, the geometrical oversizing can be omitted at the small region. As the number of regions at which the geometrical oversizing is omitted increases, the data processing time of dummy pattern generation improves significantly. As the result, using a sample data: 0.25 micrometer ASIC device wiring data with about 50 million figures, the processing time of as fast as about 1 hour 30 minutes has been achieved by the new system compared to about 2 hours and 10 minutes with the conventional system. This improvement of the processing time contributes to shorten TAT of mask data processing for ULSI.