19 July 1999 VLSI smart pixel array for free-space optical interconnects
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Proceedings Volume 3749, 18th Congress of the International Commission for Optics; (1999) https://doi.org/10.1117/12.354731
Event: ICO XVIII 18th Congress of the International Commission for Optics, 1999, San Francisco, CA, United States
Abstract
VLSI smart pixel arrays are being developed for free space optical interconnects in high density input/output applications. An individual smart pixel cell, which operates at 850 nm, consists of a vertical cavity surface emitting laser, a photodetector, an optical receiver, a laser driver, and digital logic circuitry. For optical interconnect applications, the integrated smart pixel combines high speed operation and low power consumption. A 32 X 32 smart pixel array is currently being developed that will operate at 500 Mbps/channel, which gives an aggregate throughput of > 500 Gbps with a power consumption of < 10 W.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Christine T. Mollenkopf, Christine T. Mollenkopf, Jongwoo Kim, Jongwoo Kim, John M. Hessenbruch, John M. Hessenbruch, Jack Ko, Jack Ko, Richard V. Stone, Richard V. Stone, Peter S. Guilfoyle, Peter S. Guilfoyle, } "VLSI smart pixel array for free-space optical interconnects", Proc. SPIE 3749, 18th Congress of the International Commission for Optics, (19 July 1999); doi: 10.1117/12.354731; https://doi.org/10.1117/12.354731
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