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26 October 1999 Various layouts of analog CMOS optical position-sensitive detectors
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Abstract
We report on the fabrication and characterization of analog multi-pixel optical position-sensitive detectors (PSDs) for sensing the 2D position of a light spot over the sensor area. Computer simulations were performed to understand the influence of the geometrical layout of the device on the linearity of response. Standard CMOS technology was chosen for fabrication so that the detectors are compatible with reliable low-cost and low-power electronics for integration with processing electronics. Three chessboard-like 5 X 5- pixel structures, with different pixel layouts have been implemented. The response linearity was calculated and measured over 80% of the detector active area. It was shown that chessboard-like structures are not suitable for spot diameters below 2 pixels. For a light spot diameter comparable with the device size, the best linearity of response--RMS deviation of less than 4%--among all three structures is achieved by the structure with vertical phototransistors as the photo-sensing elements. We also implemented a PSD with two complementary spiral structures, providing sensing for both coordinates in each pixel. With this layout we achieved RMS non-linearity of less than 3.5% for a spot size comparable with pixel size in close agreement to the simulations. The computer model indicates that the non-linearity for all structures studied decreases with the number of pixels.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Davies W. de Lima Monteiro, Gleb V. Vdovin, and Pasqualina M. Sarro "Various layouts of analog CMOS optical position-sensitive detectors", Proc. SPIE 3794, Materials and Electronics for High-Speed and Infrared Detectors, (26 October 1999); https://doi.org/10.1117/12.366739
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